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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a 700 mhz, 5 ma 4-to-1 video multiplexer AD8184 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 world wide web site: http://www.analog.com fax: 617/326-8703 ? analog devices, inc., 1997 product description the AD8184 is a high speed 4-to-1 multiplexer. it offers C3 db signal bandwidth of 700 mhz along with a slew rate of 750 v/ m s. with 95 db of crosstalk and 115 db isolation, it is useful in many high speed applications. the differential gain and differ- ential phase error of 0.01% and 0.01 , along with 0.1 db f latness of 75 mhz, make AD8184 ideal for professional video multi- plexing. it offers 10 ns switching time, making it an excellent choice for pixel switching (picture-in-picture) while consuming less than 4.5 ma on 5 v supply voltage. the AD8184 offers a high speed disable feature allowing the output to be put into a high impedance state. this allows mul- tiple outputs to be connected together for cascading stages while the off channels do not load the output bus. it operates on voltage supplies of 5 v and is offered in 14-lead pdip and soic packages. * all trademarks are the property of their respective holders. table i. truth table enable a1 a0 output 0 0 0 in0 0 0 1 in1 0 1 0 in2 0 1 1 in3 1 x x high z features single and dual 2-to-1 also available (ad8180 and ad8182) fully buffered inputs and outputs fast channel switching: 10 ns high speed > 700 mhz bandwidth (C3 db) > 750 v/ m s slew rate fast settling time of 15 ns to 0.1% excellent video specifications (r l > 2 k v ) gain flatness of 0.1 db of 75 mhz 0.01% differential gain error, r l = 10 k v 0.01 8 differential phase error, r l = 10 k v low power: 4.4 ma low glitch: < 25 mv low all-hostile crosstalk of C95 db @ 5 mhz high off isolation of C115 db @ 5 mhz low cost fast output disable feature for connecting multiple devices applications pin compatible with ha4314* and gx4314* video switchers and routers pixel switching for picture-in-picture switching in lcd and plasma displays functional block diagram 1 2 3 4 14 13 12 11 AD8184 enable a1 5 6 7 10 9 8 out decoder +1 +1 +1 +1 a0 +v s nc Cv s nc = no connect in0 gnd in1 in2 gnd in3 gnd frequency ?hz 1m normalized output ?db 10m 100m 1g 5 4 ? 3 2 1 0 ? ? ? ? v in = 50mvrms r l = 5k w figure 1. small signal frequency response
AD8184Cspecifications rev. 0 C2C AD8184a parameter conditions min typ max units switching characteristics channel switching time 1 channel-to-channel 50% logic to 10% output settling in0 = +1 v, in1 = C1 v 5 ns 50% logic to 90% output settling 10 ns 50% logic to 99.9% output settling 15 ns enable to channel on time 2 a0, a1 = 0 or 1 50% logic to 90% output settling in0 = +1 v, C1 v or in1 = C1 v, +1 v 12 ns enable to channel off time 2 a0, a1 = 0 or 1 50% logic to 90% output settling in1 = +1 v, C1 v or in1 = C1 v, +1 v 22 ns channel switching transient (glitch) 3 all inputs are grounded 25 mv digital inputs logic 1 voltage a0, a1 and enable inputs 2.0 v logic 0 voltage a0, a1 and enable inputs 0.8 v logic 1 input current a0, a1, enable = +4 v 10 200 na logic 0 input current a0, a1, enable = +0.4 v 2 3 m a dynamic performance C3 db bandwidth (small signal) 4 AD8184ar v in = 50 mv rms, r l = 5 k w 550 700 mhz C3 db bandwidth (large signal) AD8184ar v in = 1 v rms, r l = 5 k w 105 135 mhz 0.1 db bandwidth 4, 5 AD8184ar v in = 50 mv rms, r l = 5 k w 60 75 mhz slew rate 2 v step 600 750 v/ m s settling time to 0.1% 2 v step 15 ns distortion/noise performance differential gain ? = 3.58 mhz, r l = 2 k w 0.2 % f = 3.58 mhz, r l = 10 k w 0.01 0.02 % differential phase f = 3.58 mhz, r l = 2 k w 0.2 degrees f = 3.58 mhz, r l = 10 k w 0.01 0.02 degrees all hostile crosstalk 6 AD8184ar ? = 5 mhz C95 db ? = 30 mhz C78 db off isolation 7 AD8184ar ? = 5 mhz, r l = 30 w C115 db voltage noise ? = 30 mhz 4.5 nv/ ? hz total harmonic distortion ? c = 10 mhz, v o = 2 v p-p, r l = 1 k w C74 dbc dc/transfer characteristics voltage gain 8 v in = 1 v 0.982 v/v input offset voltage 28 mv t min to t max 15 mv input offset voltage drift 5 m v/ c input offset voltage matching channel-to-channel 0.6 3 mv input bias current 2.5 7.5 m a t min to t max 9.5 m a input bias current drift 5 na/ c input characteristics input resistance 1.0 2.4 m w input capacitance channel enabled (r package) 1.6 pf channel disabled (r package) 1.6 pf input voltage range 3.3 v output characteristics output voltage swing v in = 4 v, r l = 2 k w 9 3.15 3.2 v short circuit current 30 ma output resistance enabled 28 33 w disabled 10 m w output capacitance disabled (r package) 3.2 pf power supply operating range 4 6v power supply rejection ratio +psrr +v s = +4.5 v to +5.5 v, Cv s = C5 v 54 57 db power supply rejection ratio Cpsrr Cv s = C4.5 v to C5.5 v, +v s = +5 v 51 54 db quiescent current enabled 4.4 5.2 ma t min to t max 5.7 ma disabled 2.1 2.9 ma t min to t max 2.9 ma operating temperature range C40 +85 c (@ t a = +25 8 c, v s = 6 5 v, r l = 2 k v unless otherwise noted)
absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12.6 v internal power dissipation 2 AD8184 14-lead plastic (n) . . . . . . . . . . . . . . . . 1.6 watts AD8184 14-lead small outline (r) . . . . . . . . . . 1.0 watts input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v s output short circuit dur ation . . observe power derating curves storage temperature range n & r package . . . . . . . . . . . . . . . . . . . . . C65 c to +125 c lead temperature range (soldering 10 sec) . . . . . . . +300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 specification is for device in free air: 14-pin plastic package: q ja = 75 c/watt 14-pin soic package: q ja = 120 c/watt, where p d = (t j Ct a )/ q ja . ordering guide temperature package package model range description option AD8184an C40 c to +85 c 14-lead plastic dip n-14 AD8184ar C40 c to +85 c 14-lead narrow soic r-14 AD8184ar-reel C40 c to +85 c reel 14-lead soic r-14 AD8184-eb evaluation board for AD8184r maximum power dissipation the maximum power that can be safely dissipated by the AD8184 is limited by the associated rise in junction temperature. the maxi- mum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approxima tely +150 c. exceeding this limit temporarily may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. exceeding a junction temp erature of +175 c for an extended period can result in device failure. notes 1 enable pin is grounded. in0 and in2 = +1 v dc, in1 and in3 = C1 v dc. a0 is driven with a 0 v to +5 v pulse, a1 is grounded. measure transition time from 50% of the a0 input value (+2.5 v) and 10% (or 90%) of the total output voltage transition from in0 channel voltage (+1 v) to in1 (C1 v), or vice versa. all inputs are measured in a similar manner using a0 and a1 to select the channels. 2 enable pin is driven with 0 v to +5 v pulse (with 3 ns edges). the state of the a0 and a1 pins determines which input is activated (refer to table i). set in0 and in2 = +1 v dc, in1 and in3 = C1 v dc, and measure transition time from 50% of enable pulse (+2.5 v) to 90% of the total output voltage change. in figure 4, d t off is the disable time, d t on is the enable time. 3 all inputs are grounded. a0 input is driven with 0 v to +5 v pulse, a1 is grounded. the output is monitored. speeding the edges of the a0 pulse increases the glitch magnitude due to coupling via the ground plane. removing the a0 and a1 terminations will lower the glitch, as does increasing r l . 4 decreasing r l slightly lowers the bandwidth. increasing c l significantly lowers the bandwidth (see figure 18). 5 a resistor (r s ) placed in series with the multiplexer inputs serves to optimize 0.1 db flatness, but is not required (see figure 19.) 6 select an input that is not being driven (i.e., a0 and a1 are logic 0, in0 is selected); drive all other inputs with v in = 0.707 v rms and monitor the output at ? = 5 and 30 mhz. r l = 2 k w (see figure 12). 7 multiplexer is disabled (i.e., enable = logic 1) and all inputs are driven simultaneously with v in = 0.446 v rms. output is monitored at ? = 5 and 30 mhz. r l = 30 w to simu- late r on of one enabled multiplexer within a system (see figure 13). in this mode the output impedance is very high (typ 10 m w ), and the signal couples across the package; the load impedance determines the crosstalk. 8 voltage gain decreases for lower values of r l . the resistive divider formed by the multiplexers enables output resistance (28 w ) and r l causes a gain that increases as r l- decreases (i.e., the voltage gain is approximately 0.97 v/v [3% gain error] for r l = 1 k w ). 9 larger values of r l provide wider output voltage swings, as well as better gain accuracy. see note 8. specifications subject to change without notice. AD8184 C3C rev. 0 while the AD8184 is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction tempera- ture (+150 c) is not exceeded under all conditions. to ensure proper operation, it is necessary to observe the maximum power derating curves shown in figure 2. ambient temperature ? c 2.5 2.0 0.5 ?0 90 ?0 maximum power dissipation ?watts ?0 ?0 ?0 0 10 20 30 40 50 60 80 1.5 1.0 70 14-pin soic 14-pin dip package t j = +150 c figure 2. maximum power dissipation vs. temperature warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD8184 feature proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
C4C rev. 0 AD8184Ctypical performance curves frequency ?hz 1m normalized output ?db 10m 100m 1g 5 4 ? 3 2 1 0 ? ? ? ? v in = 50mvrms r l = 5k w r s = 0 w figure 6. small signal frequency response ?.2 0.5 0.4 0.3 0.2 0.1 0.0 ?.1 v in = 50mvrms r l = 5k w r s = 0 w normalized flatness ?db 1m 10m 100m 1g frequency ?hz ?.3 ?.4 ?.5 figure 7. gain flatness vs. frequency ?7 ? ? ?2 ?5 ?8 ?1 ?4 1m 10m 100m 1g frequency ?hz ? 0 3 output ?dbv v in = 1.0vrms r l = 5k w v in = 0.5vrms v in = 0.25vrms v in = 125mvrms v in = 62.5mvrms figure 8. large signal frequency response dut out 500mv/div 5ns/div 1v ?v output a0 pulse 0 to 5v figure 3 channel switching characteristics dut out 800mv/div ?v 10ns/div t off +1v ?v +1v t on pulse 0 to 5v figure 4. enable and disable switching characteristics 25mv/div 25ns/div output switching a0 output switching a1 a0 and a1 pulse 0 to +5v figure 5. channel switching transient (glitch)
AD8184 C5C rev. 0 50mv/div 5ns/div output @ 50mv output @ 100mv input figure 9. small signal transient response + 2v/div output = 2v + input output = 1v 10ns/div figure 10. large signal transient response 0.05 0.04 0.03 0.02 0.01 0.00 ?.01 ?.02 ?.03 ?.04 ?.05 0.05 0.04 0.03 0.02 0.01 0.00 ?.01 ?.02 ?.03 ?.04 ?.05 12 34567891011 12 34567891011 differential gain ?% differential phase ?deg r l = 2k w ntsc figure 11. differential gain and phase error frequency ?hz 100k 1g 1m 10m 100m ?0 ?0 ?10 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 crosstalk ?db v in = 0.707vrms r l = 2k w output 50 w v in 50 w 50 w AD8184 2k w 1 3 5 7 10 figure 12. all-hostile crosstalk vs. frequency off isolation ?db frequency ?hz 1g 100k 1m 10m 100m ?0 ?0 ?30 ?0 ?0 ?0 ?0 ?0 ?00 ?10 ?20 v in = 0.446 vrms r l = 30 w output 50 w v in 50 w AD8184 30 w 1 3 5 7 10 = logic 1 figure 13. off isolation vs. frequency frequency ?hz 100 10 1 10 1m 100 1k 10k 100k 10m voltage noise ?nv/ hz 30m figure 14. voltage noise vs. frequency
AD8184Ctypical performance curves C6C rev. 0 frequency ?hz 0 ?0 ?0 100k 1m 10m 100m ?0 ?0 ?0 ?0 ?0 v out = 2v p-p r l = 1k w harmonic distortion ?dbc ?0 ?0 ?00 2nd harmonic 3rd harmonic figure 15. harmonic distortion vs. frequency frequency ?hz 100m 10 100 1g 1k input and disabled output impedance 10k 100k 1m 10m 100m 10m 100k 10k 1k 100 1m z in z out (disabled) z out (enabled) 110 100 90 80 70 60 50 40 30 20 10 150 140 130 120 enabled output impedance ? w figure 16. output & input impedance vs. frequency frequency ?hz 0.03m 0.01m 10m 500m 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 pssr ?db +psrr ?srr 1m 100m figure 17. power supply rejection vs. frequency 100pf 33pf 33pf 100pf 10pf 0pf normalized flatness ?db frequency ?hz 1m 10m 100m 1g 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 ?.1 ?.2 normalized output ?db ? ? ? ? ? ? ? ? ? 0 1 v in = 50mvrms r l = 5k w r s = 0 w figure 18. frequency response vs. capacitive load 0.3 0.2 0.1 normalized flatness ?db v in = 50mvrms r l = 5k w r s = 150 w 10m 100m frequency ?hz 1m ?.2 ?.1 0 0.4 0.5 1g r s = 0 w r s = 75 w r s = 0 w r s = 75 w r s = 150 w 0.6 0.7 0.8 ? ? ? ? ? ? ? ? ? 0 1 normalized output ?db figure 19. frequ ency response vs. input series resistance input voltage ?volts 5 ? ? ? 5 ? ? ? ? 0 1 2 3 4 4 0 ? ? 2 1 ? 3 output voltage ?volts figure 20. output voltage vs. input voltage, r l = 2 k w
AD8184 C7C rev. 0 series resistors at the input or output. if better flatness response is desired, an input series resistance (r s ) may be used (refer to figure 19), although this will increase crosstalk. the dc gain of the AD8184 is almost independent of load for r l > 10 k w . for heavier loads, the dc gain is approximately that of the voltage divider formed by the output impedance of the mux (typically 28 w and r l ). high speed disable clamp circuits (not shown) at the bases of q3 and q4 allow the buffers to turn off quickly and cleanly without dissipating much power once off. moreover, these clamps shunt displacement currents flowing through the junc- tion capacitances of q1 and q2 away from the bases of q3 and q4 and to ac ground through low impedances. the two-pole high-pass frequency response of the t switch formed by these clamps is a significant improvement over the one-pole high pass response of a simple series cmos switch. as a result, board and package parasitics, especially stray capacitance between inputs and outputs, may limit the achievable crosstalk and off isolation. layout considerations: realizing the high speed performance attainable with the AD8184 requires careful attention to board layout and compo- nent selection. proper rf design techniques and low parasitic component selection are mandatory. wire wrap boards, prototype boards and sockets are not recom- mended because of their high parasitic inductance and capaci- tance. instead, surface-mount components should be directly soldered to a printed circuit board (pcb). the pcb should have a ground plane covering all unused portions of the compo- nent side of the board to provide a low impedance ground path. to reduce stray capacitance the ground plane should be removed from the area near input and output pins. theory of operation the AD8184 video multiplexer is designed for fast switching (10 ns) and wide bandwidth (> 700 mhz). this performance is attained with low power dissipation (4.4 ma, enabled) through the use of proprietary circuit techniques and a dielectrically- isolated complementary bipolar process. this device has a fast disable function that allows the outputs of several muxes to be wired in parallel to form a larger mux with little degradation in switching time. the low disabled output capacitance (3.2 pf) helps to preserve the system bandwidth in larger matrices. un- like earlier cmos switches, the switched open-loop buffer ar- chitecture of the AD8184 provides a unidirectional signal path with minimal switching glitches and constant, low input capaci- tance. since the input impedance of these muxes is nearly inde- pendent of the load impedance and the state of the mux, the frequency response of the on channels in a large switch matrix is not affected by fanout. figure 21 shows a block diagram and simplified schematic of the AD8184, which contains four switched buffers (s0Cs3) that share a common output. the decoder logic translates ttl- compatible logic inputs (a0, a1 and enable ) to internal, dif- ferential ecl levels for fast, low-glitch switching. the a0 (lsb) and a1 (msb) control inputs constitute a two-bit binary word that determines which of the four buffers is enabled, unless the enable input is high, in which case all buffers are disabled and the output is switched to a high impedance state. each open-loop buffer is implemented as a complementary emitter follower that provides high input impedance, symmetric slew rate and load drive, and high output-to-input isolation due to its b 2 current gain. the selected buffer is biased on by fast switched current sources that allow the buffer to turn on quickly. dedicated flatness circuits, combined with the open-loop archi- tecture of the AD8184, keep peaking low (typically < 0.5 db) when driving high capacitive loads, without the need for external AD8184 1 in0 s3 i1 i2 q2 q1 q3 q4 6 s2 i1 i2 q2 q1 q3 q4 s1 i1 i2 q2 q1 q3 q4 s0 i1 i2 q2 q1 q3 q4 decoder 2 gnd 3 in1 5 in2 gnd 4 gnd 7 in3 14 13 12 11 10 9 8 v ee nc out a1 a0 v cc nc = no connect figure 21. block diagram and simplified schematic of the AD8184 multiplexer
AD8184 C8C rev. 0 chip capacitors should be used for supply bypassing. one end of the capacitor should be connected to the ground plane and the other within 1/4 inch of each power pin. an additional large (4.7 m fC10 m f) tantalum capacitor should be connected in par- allel with each of the smaller capacitors for low impedance sup- ply bypassing over a broad range of frequencies. signal traces should be as short as possible. stripline or microstrip techniques should be used for long (longer than about 1 inch) signal traces. these should be designed with a characteristic impedance of 50 w or 75 w and be properly ter- minated at each end using surface mount components. careful layout is imperative to minimize crosstalk. guards (ground or supply traces) must be run between all signal traces to limit direct capacitive coupling. input and output signal lines should fan out away from the mux as much as possible. if mul- tiple signal layers are available, a buried stripline structure hav- ing ground plane above, below and between signal traces will have the best crosstalk performance. return currents flowing through termination resistors can also increase crosstalk if these currents flow in sections of the finite- impedance ground circuit shared between more than one input or output. minimizing the inductance and resistance of the ground plane can reduce this effect, but further care should be taken in po- sitioning the terminations. terminating cables directly at the con- nectors will minimize the return current flowing on the board, but the signal trace between the connector and the mux will look like an open stub and will degrade the frequency response. moving the termination resistors close to the input pins will improve the fre- quency response, but the terminations from neighboring inputs should not have a common ground return. applications a buffered 4-to-1 multiplexer in applications where the output of a multiplexer must drive a back-terminated 75 w line (r l = 75 w + 75 w ), it is necessary to buffer the output of the AD8184. in the example in figure 22, this is accomplished using the ad8009 high speed current feedback op amp. the amplifier is configured with a gain of 2 to compensate for the signal halving due to termination at the multi- plexer input. this gives the overall circuit a gain of unity. if lower speed can be tolerated, a number of other amplifiers can replace the ad8009 op amp in the above circuit. in general there is a trade-off between bandwidth and power consumption. table ii summarizes the bandwidth and power consumption characteristics of these op amps. table ii. amplifier options for multiplexer buffering op amp comments ad8009 highest bandwidth, (g = +2) = 700 mhz, i sy = 14 ma ad8001 lower power consumption, bandwidth (g = +2) = 440 mhz, i sy = 5 ma ad8011 lower power consumption, bandwidth (g = +2) = 210 mhz, i sy = 1 ma ad8079 fixed gain dual amplifier (2 or 2.2), bandwidth = 260 mhz, i sy = 5 ma per amp ad8005 lowest power consumption, bandwidth (g = +2) = 170 mhz, i sy = 400 m a ? s 681 w +1 decoder 1 2 3 4 5 6 7 14 13 12 11 10 9 8 +1 +1 +1 AD8184 75 w 75 w 75 w 75 w +v s nc ? s gnd gnd gnd 0.1? 10? v out 0.1? 10? 10? 0.1? +v s +v s 10? 0.1? a0 a1 75 w ? s 681 w ad8009 in0 in1 in2 in3 figure 22. a buffered 4-to-1 multiplexer
AD8184 C9C rev. 0 color document scanner figure 23 shows a block diagram of a color document scanner. charge coupled devices (ccds) find widespread use in scan- ner applications. a monochrome ccd delivers a serial stream of voltages levels, each level being proportional to the light shin- ing on that cell. in the case of the color image scanner shown, there are three output streams, representing red, green and blue. interlaced with the stream of voltage levels is a voltage repre- senting the reset level (or black level) of each cell. a correlated double sampler (cds) subtracts these two voltages from each other in order to eliminate the relatively large offsets common with ccds. control & timing cds cds 0.1? 10? v in b v ref sense v in a ad9220 10/12-bit 10msps a/d converter out cds a1 a0 AD8184 r g enable b ccd reference figure 23. color document scanner the next step in the data acquisition process involves digitizing the three signal streams. assuming that the analog-to-digital converter chosen has a fast enough sample rate, multiplexing the three streams into a single adc is generally more economi- cal than using one adc per channel. in the example shown, we use the AD8184 as the multiplexer. because of its high bandwidth, the AD8184 is capable of driving the switched capacitor input stage of the ad9220 without addi- tional buffering. in addition to having the required bandwidth, it is necessary to consider the settling time of the multiplexer. in this case, the adc has a sample rate of 10 mhz, which corre- sponds to a sampling period of 100 ns. typically, one phase of the sampling clock is used for conversion (i.e., all levels are held steady) and the other is used for switching and settling to the next channel. assuming a 50% duty cycle, the signal chain must settle within 50 ns. with a settling time to 0.1% of 15 ns, the multiplexer easily satisfies this criterion. in the example shown, the fourth (spare) channel of the AD8184 is used to measure a reference voltage. this voltage would probably be measured less frequently than the r, g and b signals. multiplexing a reference voltage offers the advantage that any temperature drift effects caused by the multiplexer will equally impact the reference voltage and the to-be-measured sig- nals. if the fourth channel is unused, it is good design practice to permanently tie it to ground. a 4 3 4 crosspoint switch while large crosspoint arrays are best constructed using highly integrated devices such as the ad8116, 16 16 crosspoint switch, smaller or irregular sized arrays can be constructed using 4-to-1 multiplexers such as the AD8184. the circuit below shows a 4 4 array, constructed using the AD8184 and buff- ered using the ad8079, a dual, fixed gain of 2 or 2.2, video amplifier. 750 w 750 w out 1/2 ad8079* AD8184 in0-in3 out0 750 w 750 w out 1/2 ad8079* AD8184 in0-in3 out1 750 w 750 w out 1/2 ad8079* AD8184 in0-in3 out2 750 w 750 w out 1/2 ad8079* AD8184 in0-in3 out3 in0-3 4 4 4 4 4 *ad8079 is a dual, fixed gain of 2 amplifier figure 24. 4 4 crosspoint switch
AD8184 C10C rev. 0 ? s +1 decoder 1 2 3 4 5 6 7 14 13 12 11 10 9 8 +1 +1 +1 AD8184 r3 49.9 w +v s nc ? s gnd gnd gnd 0.1? 10? +v s 10? 0.1? in0 in1 in2 in3 c2 c1 a0 a1 out (scope probe adapter) r5 49.9 w r6 49.9 w r7 49.9 w r8 4.99k w r2 49.9 w r1 49.9 w r4 49.9 w c4 c3 figure 25. AD8184ar evaluation board evaluation board an evaluation board is available for the AD8184. it has been carefully laid out and tested to demonstrate the specified high speed performance of the devices. figure 25 shows the sche- matic of the evaluation board. for ordering info rmation, please refer to the ordering guide. figure 26 shows the silkscreen of the component side and fig- ure 28 shows the silkscreen of the solder side. figures 27 and 29 show the layout of the component side and solder side respectively. the evaluation board is provided with 49.9 w termination resis- tors on all inputs. this is to allow the performance to be evalu- ated at very high frequencies where 50 w termination is most popular. to use the evaluation board in video applications, the termination resistors should be replaced with 75 w resistors. the fr4 board type has the following stripline dimensions: 60-mil width, 12-mil gap between center conductor and outside ground plane island and 62-mil board thickness. the multiplexer output is loaded with a 4.99 k w resistor. for connection to external instruments, an oscilloscope probe adapter is provided. this allows direct connection of an fet probe to the board. for verification of data sheet specifications, use of an fet probe is recommended because of its low input capacitance. the probe adapter used on the board has the same footprint as sma, smb and smc type connectors, allowing easy replacement if necessary. the side-launched sma connectors on the analog and digital inputs can also be replaced by top-mount sma, smb or smc type connectors. when using top-mount connectors, the stripline on the outside 1/8" of the board edge should be re- moved with an x-acto blade as this unused stripline acts as an open stub, which could degrade the small-signal frequency re- sponse of the multiplexer. input termination resistor placement on the evaluation board is critical to reducing crosstalk. each termination resistor is ori- ented so that the ground return currents flow counterclockwise to the ground plane island. although the direction of this ground current flow is arbitrary, it is important that no two in- put or output termination resistors share a connection to the same ground island.
AD8184 C11C rev. 0 figure 26. component side silkscreen figure 27. board layout (component side) figure 28. solder side silkscreen figure 29. board layout (solder side)
AD8184 C12C rev. 0 c3036C10C4/97 printed in u.s.a. C12C outline dimensions dimensions shown in inches and (mm). 14-lead plastic dip (n-14) 14 17 8 0.795 (20.19) 0.725 (18.42) 0.280 (7.11) 0.240 (6.10) pin 1 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) seating plane 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.160 (4.06) 0.115 (2.93) 14-lead soic (r-14) 14 8 7 1 0.3444 (8.75) 0.3367 (8.55) 0.2440 (6.20) 0.2284 (5.80) 0.1574 (4.00) 0.1497 (3.80) pin 1 seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0688 (1.75) 0.0532 (1.35) 0.0500 (1.27) bsc 0.0099 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) x 45

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